Elite Semiconductor Microelectronics Technology Inc. (ESMT) to Showcase Revolutionary aiPIM (DRAM Processing-in-Memory) Architecture at Computex 2026

[TAIPEI, TAIWAN] – ESMT, a leading global provider of innovative memory solutions, today announced that it will join forces with industry pioneers Cadence, AP Memory, and the Industrial Technology Research Institute (ITRI) at the upcoming Computex 2026 to showcase the groundbreaking aiPIM: DRAM Processing-in-Memory Technology Platform. Tailor-made for the edge AI era, this innovative architecture is designed to break the high-power, bandwidth-constrained "von Neumann bottleneck," unleashing the ultimate potential of edge devices.

As Transformer algorithms and lightweight LLMs (Large Language Models) proliferate across terminal devices, traditional architectures face severe memory-bound latency and power consumption challenges due to frequent data movement. ESMT has addressed this by introducing a pragmatic, "Drop-and-Play" strategy. This seamless upgrade path for existing edge systems requires zero data duplication and zero hardware interface modifications, significantly reducing the depreciation rate of legacy equipment in the AI era while offering immediate AI scalability.

Core Technical Highlights of aiPIM:

· Leading 3D Stacking Technology: Utilizing 3D Wafer-on-Wafer (WoW) technology, the logic computation layer is vertically bonded. Products scale across different capacity levels using 1GB DRAM as the base unit. Beneath the 1GB DRAM die, a massive matrix of TSVs (Through-Silicon Vias) connects to the high-frequency, 1024-bit wide AXI bus of the logic die for ultra-efficient data exchange. By optimizing data movement at the physical layer, this 3D direct connection reduces data transfer energy consumption by up to 1,000 times compared to traditional DRAM interfaces.

· "Drop-and-Play" Compatibility: Supporting standard LPDDR4/5 and xSPI interfaces, customers can reuse existing MCU/CPU DRAM controllers. Legacy systems can be directly replaced and upgraded without interface modifications, achieving ultra-low-cost AI enablement. The system-on-chip not only frees up valuable PCIe resources, but also leverages direct memory access to eliminate the IO transition latency caused by frequent user/kernel space switching in traditional AI accelerator sticks.

· AI Task-Oriented Green Software Architecture: Moving away from complex, fragmented instruction sets, the platform adopts a mailbox communication mechanism. Acting as an Execution Provider, it seamlessly integrates mainstream edge inference frameworks—including Microsoft ONNX Runtime, Ollama GGML, and Google LiteRT—without interfering with the original proprietary CPU toolchains.

Building an Open 3D PIM Ecosystem Alliance:

Recognizing that hardware and software standardization is critical to the commercialization of PIM, ESMT has partnered with top-tier industry leaders to build an open platform:

1. Cadence: Introducing Generative AI-driven IC design to accelerate the development and iteration of PIM chips.

2. AP Memory: Leveraging VHM™ (Very High Bandwidth Memory) technology to provide a powerful, high-bandwidth memory foundation.

3. ITRI: Deeply collaborating on the development of LLM-optimized NPUs, software stacks, and development toolkits, culminating in the joint creation of the first 3D aiPIM test chip.

Invitation to Visit:

ESMT will showcase the live aiPIM architecture at Computex 2026. We cordially invite global system integrators, hardware/software developers, and industry media to visit our booth. Come explore how 3D PIM technology can inject powerful new momentum into smart doorbells, industrial handheld terminals, and humanoid robots!

· Exhibition Dates: June 2 – June 5, 2026

· Venue: Taipei Nangang Exhibition Center, Hall 1, 1F (TaiNEX 1)

· Exhibition Zone: AI Computing & Technology Zone

· Booth Number: Booth # J0517a

WHAT’S NEWS

Elite Semiconductor Microelectronics Technology Inc. (ESMT) to Showcase Revolutionary aiPIM (DRAM Processing-in-Memory) Architecture at Computex 2026